As is known in the art, one type of focal plane array includes a semiconductor wafer having an array of electromagnetic radiation detectors, such as infrared detectors or optical energy detectors, flip chip bonded to a semiconductors wafer having read out integrated circuit (ROIC) electronics for processing the energy detected by the detectors.
More particularly, with a cold (i.e., room temperature) compression bonding technique, a flip chip single die to die bonding process is used consisting of two steps: alignment of the two wafers, followed by a cold compression pressing illustrated in FIG. 1, which forms the mechanical and electrical interconnect. More particularly, a solid chuck (FIG. 1) presses the aligned parts (i.e., the detector die to the ROIC die) together; however, because the semiconductor wafer having an array of electromagnetic radiation detectors is not perfectly flat, (i.e., non-uniform), applying pressure at the high points (i.e., stress points indicated by the stars in FIG. 1) of the back of the detector wafer or thicker sections of the hybrid stack results in areas where interconnection is not achieved until stack is sufficiently deformed to allow low areas (thinner substrate) the chance to achieve interconnection, For large die, the long bonding time and the tight flatness requirement results in higher cost due to increased time on the precision aligner and more stringent requirements on the flatness of incoming detector die and readout Integrated Circuits (ROIC) die/components.
In standard reflow flip-chip bonding, the die are aligned and the electrical contacts of the detectors and the elements of the ROIC are vertically stacked; then the contacts are melted together to form a bond. This method is difficult in Infrared (IR) Sensor Chip Assembly (SCA) hybridization due to mismatches in coefficient of thermal expansion between detector and ROIC materials and ever decreasing pixel pitches.
An interconnect approach using oxide and/or metallic bonding to connect multiple die to a wafer may be used; however, these process are difficult to integrate with many Infrared detector materials.
Thus, in summary: (1) the use of flip chip cold compression bonding requires a very flat die which decreases yield of incoming components and increases cost; is relatively time intensive; requires significant amount of time on high precision (expensive) aligner; and is limited to single die hybridization which limits throughput and potential cost savings from batch processing; (2) reflow bonding, high throughput wafer level solutions rely on solder bonding at elevated temperatures and the higher temperature processing is not compatible with most IR materials due to mismatch in coefficient of thermal expansion and fine pixel pitch spacing; also reflow bonding requires very flat die which decreases yield of incoming components and increases cost; and (3) Oxide and/or metallic bonding techniques are not compatible with IR materials, particularly column III-V materials, due to material incompatibility with high temperatures and would require very flat die/wafers which decrease yield of incoming components and wafer cost.